FIG. 1 of the accompanying drawings is a circuit diagram of a known source coupled logic gate performing a NOR/NAND function, consisting of a transistor current source (10) with its drain connected to the common source nodes of two bottom-level switching transistors (21, 22), the gate nodes of which are the bottom-level inputs (PC, NC) of the logic gate. Their drain nodes are connected either to one of the two top-level outputs of the input stage (PT, NT) or the source nodes of the top-level switching transistors (31, 32). The gate nodes of transistors 31 and 32 are the top-level inputs of the logic gate (PA, NA) and their drain nodes are connected to said top-level outputs of the input stage which in turn are connected to the positive power supply voltage node (VDD) through the simple resistive load elements (41, 42) as well as to the inputs of two buffer/level shifters for driving the following gate top-level and bottom-level inputs.
The present invention aims to reduce the power dissipation and complexity of the known source coupled logic gate configuration and to provide an efficient means for the implementation of logic functions, utilizing Field Effect Transistors with the presence of Schottky diode at the gate region.
The source coupled logic gate configuration utilizing Field Effect Transistors with the presence of Schottky diode at the gate region comprises an input stage for the implementation of a given logic function followed by buffer/level shifters.